pyrpl.test.test_attribute.
DummyModule
(parent, name=None)[source]¶Bases: pyrpl.modules.Module
Setup Attributes:
setup
(**kwds)¶Sets the module up for acquisition with the current setup attribute values.
sub2
¶sub1
¶some_filter
¶some_number
¶some_options
¶Options – [‘foo’, ‘bar’]
sub1
sub2
true_or_false
¶pyrpl.test.test_attribute.
FirstSubModule
(parent, name=None)[source]¶Bases: pyrpl.modules.Module
Setup Attributes:
b1
¶b2
¶setup
(**kwds)¶Sets the module up for acquisition with the current setup attribute values.
b1
b2
pyrpl.test.test_attribute.
MyFilterProperty
(default=None, doc='', ignore_errors=False, call_setup=False)[source]¶pyrpl.test.test_load_save.
TestLoadSave
[source]¶Bases: pyrpl.test.test_base.TestPyrpl
iterates over all modules, prepares a certain state, saves this, messes up the current state, loads the saved state and checks whether attributes are the ones that were saved
pyrpl.test.test_load_save.
scramble_values
(mod, str_val='foo', num_val=12.0, bool_val=True, list_val=[1912], option_index=0, list_length=4)[source]¶This function tries to modify all _setup_attributes of the module mod
.
The arguments specify the new values for each type of Attribute.
Parameters: |
|
---|---|
Returns: | lists of all modified attribute names and the set values. |
Return type: | attr_names, attr_vals |
pyrpl.test.test_memory.
TestMemory
[source]¶Bases: object
test_two_trees
()[source]¶makes two different memorytree objects that might have conflicts w.r.t. each other.
The conflicts arise from the latency between the objects in memory and the file defined by _loadsavedeadtime for speed reasons.
pyrpl.test.test_na.
TestNA
[source]¶Bases: pyrpl.test.test_base.TestPyrpl
test_iq_autosave_active
()[source]¶At some point, iq._autosave_active was reinitialized by iq create_widget...
pyrpl.test.test_proxyproperty.
MyModule
(parent, name=None)[source]¶Bases: pyrpl.modules.Module
Setup Attributes:
moduleproperty
¶myfloat
¶myfloatproxy
¶myselectproxy
¶setup
(**kwds)¶moduleproperty
pyrpl.test.test_proxyproperty.
MySubModule
(parent, name=None)[source]¶Bases: pyrpl.modules.Module
Setup Attributes:
myfloat
¶myselect
¶Options – [1, 2, 3, ‘a’, ‘b’, ‘c’]
setup
(**kwds)¶Sets the module up for acquisition with the current setup attribute values.
pyrpl.test.test_pyqtgraph_benchmark.
TestPyqtgraph
[source]¶Bases: pyrpl.test.test_redpitaya.TestRedpitaya
This test case creates a maximally simplistic scope gui that continuously plots the data of both scope channels, and checks the obtainable frame rate. Frame rates down to 20 Hz are accepted
N
= 16384¶REDPITAYA
= False¶cycles
= 50¶dt
= 0.01¶duration
= 1.0¶frequency
= 10.0¶timeout
= 10.0¶pyrpl.test.test_registers.
TestRegisters
[source]¶Bases: pyrpl.test.test_redpitaya.TestRedpitaya
This test verifies that all registers behave as expected.
The test is not only useful to test the python interface, but also checks that the fpga is not behaving stragely, i.e. loosing data or writing the wrong data. Thus, it is the principal test to execute on new fpga designs.
pyrpl.test.test_spectrum_analyzer.
TestClass
[source]¶Bases: pyrpl.test.test_base.TestPyrpl
test_iq_filter_white_noise
()[source]¶Measure the transfer function of an iq filter by measuring the cross-spectrum between white-noise input and output
test_no_write_in_config
()[source]¶Make sure the spec an isn’t continuously writing to config file, even in running mode. :return:
test_white_noise_flatness
()[source]¶Make sure a white noise results in a flat spectrum, with a PSD equal to <V^2> when integrated from 0 Hz to Nyquist frequency. To make sure no aliasing problem occurs, a narrowbandpass filter is used. The test cannot be perfomed for the largest bandwidth because then the transfer function correction for the scope decimation should not be applied for internal signals (however, the sinc correction is applied in practice).