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PyRPL
0.9.4.0
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Installation
Graphical user interface
API
How PyRPL works
Infos for Developers
Full documentation structure
Full documentation structure
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1. Installation
1.1. Preparing the hardware
1.2. Installing PyRPL
1.3. Compiling the FPGA code (optional)
2. GUI instruments manual
2.1. Video tutorial
2.2. Starting the GUI
2.3. A typical module widget: PID module
2.4. Acquisition Module Widgets
2.4.1. Scope Widget
2.4.2. Network Analyzer Widget
2.4.3. Spectrum Analyzer Widget
2.5. Iq Widget
2.5.1. Pound Drever Hall signal generation
2.5.2. Network analyzer
2.5.3. Phase-frequency detector
2.5.4. Tuanble bandpass filter
2.6. Lockbox Widget
3. API manual
3.1. 1 First steps
3.1.1. Connecting to the RedPitaya
3.1.2. Basic communication with your RedPitaya
3.2. 2 RedPitaya (or Hardware) modules
3.2.1. ASG and Scope module
3.2.2. Arbitrary Signal Generator
3.2.3. Oscilloscope
3.2.4. PID module
3.2.4.1. Proportional and integral gain
3.2.4.2. Control with the integral value register
3.2.4.3. Input filters
3.2.5. IQ module
3.2.5.1. Network analyzer
3.2.5.2. Lorentzian bandpass filter
3.2.5.3. Frequency comparator module
3.2.6. IIR module
3.3. 3 Pyrpl (or Software) modules
3.3.1. Using Module Managers
3.3.2. Spectrum Analyzer
3.3.3. Lockbox
4. Basics of the PyRPL Architecture
4.1. Motivation
4.2. Hardware Platform - Red Pitaya
4.3. Software Infrastructure
4.3.1. FPGA modules
4.3.2. Monitor Server
4.3.3. Python package PyRPL
4.3.3.1. The Module class
4.3.3.2. The Proprety descriptors
4.3.3.3. Module states
4.3.3.4. Automatic GUI creation
4.3.3.5. Example: definition of the Pid class
5. Notes for developers
5.1. Contributing to PyRPL
5.2. Building the FPGA firmware
5.2.1. Compiling the FPGA code
5.2.2. How to get the right license for Vivado 2015.4
5.3. Unittests
5.4. Coding style guidelines
5.4.1. General guidelines
5.4.2. Naming conventions
5.4.3. Docstrings
5.5. Workflow to submit code changes
5.5.1. Preliminaries
5.5.2. Use git to collaborate on code
5.6. API specifications from the moment of their development
5.6.1. Requirements for an asynchronous interface compatible with python 3 asyncio
5.6.1.1. asynchronous programming in python 3
5.6.1.2. Can we make that compatible with python 2
5.6.1.3. Asynchronous sleep function benchmarks
5.6.2. Asynchronous sleep function and benchmarks
5.6.2.1. Methods compatible with python 2:
5.6.2.1.1. The normal time.sleep function (which is not asynchronous)
5.6.2.1.2. Constantly calling APP.processEvents()
5.6.2.1.3. Running the QEventLoop locally
5.6.2.1.4. The hybrid approach
5.6.2.1.5. Benchmark in the presence of other events
5.6.2.1.5.1. time.sleep
5.6.2.1.5.2. calling processEvents
5.6.2.1.5.3. running the eventLoop locally
5.6.2.1.5.4. our custom function
5.6.2.2. Async programming in python3(.5):
5.6.3. How a spectrum is computed in PyRPL
5.6.3.1. Definitions
5.6.3.2. Sinusoidal input
5.6.3.3. White noise input
5.6.3.4. IQ mode
5.6.3.5. Baseband
5.6.3.6. Proposal for a cleaner interface for spectrum analyzer:
5.6.3.7. IQ mode with proper anti-aliasing filter
5.6.4. MemoryTree
5.6.4.1. Problems
5.6.5. Base classes Attributes and Module
5.6.5.1. Module (see BaseModule in module.py)
5.6.5.1.1. public methods
5.6.5.1.2. Public attributes:
5.6.5.1.3. class attributes to be implemented in derived class:
5.6.5.1.4. methods to implement in derived class:
5.6.5.2. Attributes
5.6.6. Starting to rewrite SelectAttribute/Property
5.6.7. AcquisitionModule
5.6.7.1. A proposal for a uniformized API for acquisition modules (Scope, SpecAn, NA)
5.6.7.1.1. Synchronous mode:
5.6.7.1.2. Asynchronous mode
5.6.7.1.3. public methods (All methods return immediately)
5.6.7.1.4. Public attributes:
5.6.8. Lockbox
5.6.9. DataWidget
5.7. Distribution of pyrpl
5.7.1. How to generate the automatic documentation with Sphinx
5.7.2. How to make a single-file pyrpl executable not depending on a Python installation
5.7.3. Prepare a new release
5.8. SD card preparation
5.8.1. Option 1: flash the full image at once
5.8.2. Option 2: Format and copy a list of files on the SD card
